1. Field of the Invention
The invention relates to semiconductor devices, and in particular, to trig modulation electrostatic discharge (ESD) protection devices.
2. Description of the Related Art
Conventional high voltage electrostatic discharge (ESD) protection devices include lateral diffused metal oxide semiconductor (LDMOS) power transistors, metal oxide semiconductor field effect transistors (MOSFET), silicon control rectifiers (SCR), bipolar junction transistors (BJT), diodes and field oxide devices (FOD). For ESD protection during high voltages, an inner circuit may either be damaged or result in a latch-up effect due to an over-high trigger voltage and an over-low holding voltage. Therefore, by adding an additional driving circuit, or by regulating layout parameters, trig voltage can be reduced such that a holding voltage of a device can be higher than an operation voltage. Thus, resulting in a high voltage electrostatic discharge (ESD) protection device.
FIG. 1 is a schematic diagram illustrating the relationship between voltage and current of a conventional high voltage ESD protection device. Because the holding voltage Vh of the conventional high voltage ESD protection device cannot reach higher than the operation voltage VDD of the circuit, it is therefore desirable to increase the holding voltage Vh of the ESD protection device such that the holding voltage is maintained over the operation voltage VDD, as shown by the dash line of FIG. 1. By increasing the holding voltage Vh, however, the trig voltage Vtrig of the ESD protection device is also increased. Thus, the dilemma of trying to hold the trig voltage Vtrig of the ESD protection device at a low level.
The conventional method for reducing the trig voltage of the ESD protection device is by augmenting the base-emitter resistance RBE of the parasitic BJT device, i.e., extending the distance between the source and the bulk. However, enlarging the distance between the source and the bulk does not result in a major effect, increases layout area of the device, and hinders device integration.
FIG. 2A is a cross section of a conventional ESD protection device. Referring to FIG. 2A, a conventional ESD protection device 10 includes a p-type semiconductor substrate 11. A high voltage n-type well region 12 is formed in the p-type semiconductor substrate 11. An n-type drain drifted region (NDD) 14 and a p-type body doped region 15 are disposed in the high voltage n-type well region 12, wherein the n-type drain drifted region (NDD) 14 and the p-type body doped region 15 are separated by an isolation 13a. An n-type drain doped region 16 is disposed in the n-type drain drifted region (NDD) 14. An n-type heavily doped region 17 and a p-type heavily doped region 18 are disposed in the p-type body doped region 15, wherein the n-type heavily doped region 17 and the p-type heavily doped region 18 are separated by an isolation 13b. A gate 19 is disposed between the n-type heavily doped region 17 and the isolation 13a. The ESD protection device 10 is isolated from other devices in the circuit by an isolation 13c. During operation, the n-type drain doped region 16 is coupled to the operation voltage VDD of the circuit. The gate 19, the n-type heavily doped region 17, and the p-type heavily doped region 18 are coupled to a voltage VSS or a ground. Therefore, the abovementioned ESD protection device 10 is also referred to as a gate ground NMOS (GGNMOS) transistor device.
FIG. 2B is a cross section of another conventional ESD protection device. In FIG. 2B, the conventional ESD protection device 20 includes a p-type semiconductor substrate 21. A high voltage n-type well region 22 is formed in the p-type semiconductor substrate 21. An n-type drain drifted region (NDD) 24 and a p-type body doped region 25 are disposed in the high voltage n-type well region 22, wherein the n-type drain drifted region (NDD) 24 and the p-type body doped region 25 are separated by an isolation 23a. An n-type drain doped region 26 is disposed in the n-type drain drifted region (NDD) 24. An n-type heavily doped region 27 and a p-type heavily doped region 28 are disposed in the p-type body doped region 25. A gate 29 is disposed between the n-type heavily doped region 27 and the isolation 23a. The ESD protection device 20 is isolated from other devices in the circuit by an isolation 23c. During operation, the n-type drain doped region 26 is coupled to the operation voltage VDD of the circuit and coupled to a first end of a capacitor. Both the n-type heavily doped region 27 and the p-type heavily doped region 28 are coupled to a voltage VSS or a ground. The gate 29 is coupled to a second end of the capacitor and coupled to a first end of a resistor. Therefore, the abovementioned ESD protection device 20 is also referred as a capacitive ESD protection device.
FIG. 3A is a cross section of another conventional ESD protection device, which increases the base-emitter resistance RBE of the parasitic BJT device and maintains advantages of the capacitive ESD protection devices. Referring to FIG. 3A, the conventional ESD protection device 50 includes a p-type semiconductor substrate 51. A high voltage n-type well region 52 is formed in the p-type semiconductor substrate 51. An n-type drain drifted region (NDD) 54 and a p-type body doped region 55 are disposed in the high voltage n-type well region 52, wherein the n-type drain drifted region (NDD) 54 and the p-type body doped region 55 are separated by an isolation 53a. An n-type drain doped region 56 is disposed in the n-type drain drifted region (NDD) 54. An n-type heavily doped region 57 and a p-type heavily doped region 58 are disposed in the p-type body doped region 55, wherein the n-type heavily doped region 57 and the p-type heavily doped region 58 are separated by an isolation 53b. A gate 59 is disposed between the n-type heavily doped region 57 and the isolation 53a. The ESD protection device 50 is isolated from other devices in the circuit by an isolation 53c. During operation, the n-type drain doped region 56 is coupled to the operation voltage VDD of the circuit and coupled to a first end of a capacitor. Both the n-type heavily doped region 57 and the p-type heavily doped region 58 are coupled to a voltage VSS or a ground. The gate 59 is coupled to a second end of the capacitor and coupled to a first end of a resistor. The equivalent circuit diagram of the ESD protection device 50 is shown in FIG. 3B. However, the enlarged distance between the source and the bulk only slightly increases the base-emitter resistance RBE of the parasitic BJT device 65, and does not effectively reduce the trig voltage thereof. Moreover, the layout area of the device is undesirably increased, which is detrimental to scaling down of the device layout as well as integration with other devices.